This invention relates to a method of manufacturing a semiconductor device comprising a bipolar transistor and an insulated gate field effect transistor and especially, but not exclusively, to a method of manufacturing a semiconductor device comprising a bipolar transistor and complementary insulated gate field effect transistors (IGFETs), that is a so-called BiCMOS device.
U.S. Pat. No. 4,752,589 describes a method of manufacturing a semiconductor device comprising a bipolar transistor and an insulated gate field effect transistor, which method comprises providing a semiconductor body having, adjacent to one major surface, a collector region of one conductivity type at a first device area and a first well region of the one conductivity type at a second device area, defining an insulated gate on the second device area, introducing impurities to form source and drain regions of the opposite conductivity type in the first well region, providing a layer doped with impurities of the opposite conductivity type on the first device area for forming an extrinsic base region, providing an insulating layer to cover the doped layer, forming an opening through the insulating and doped layers to expose a surface region of the first device area, and introducing impurities for forming an intrinsic base region of the opposite conductivity type and an emitter region of the one conductivity type within the intrinsic base region.
The method described in U.S. Pat. No. 4,752,589 also enables the manufacture in a third device area of an insulated gate field effect transistor of the one conductivity type to enable complementary, that is n-channel and p-channel insulated gate field effect transistors or MOSTs within respective complementary conductivity type well regions, to form a so-called BiCMOS device.
In the specific example described in U.S. Pat. No. 4,752,589, a buried region technology is used with the collector region and the well region of the one conductivity type being formed in an epitaxial layer of the opposite conductivity type and each contacting a respective highly doped buried region of the one conductivity type formed at the surface of the underlying opposite conductivity type substrate.
After definition of the device areas and formation of the collector and well regions, the doped layer and covering insulating layer for providing the extrinsic base region are provided. The opening is then formed by defining a first window through the insulating and doped layers and the impurities for forming the intrinsic base region are implanted. Subsequently, by anisotropically etching a deposited insulating layer, insulating regions are provided on the edges of the doped layer for forming a smaller second window through which the impurities for forming the emitter are introduced. After introduction of the emitter-forming impurities, the introduced impurities are caused to diffuse to form the extrinsic and intrinsic base regions and the emitter region.
In addition in the method described in U.S. Pat. No. 4,752,589, the formation of the complementary insulated gate field effect transistors occurs during the formation of the bipolar transistor. In particular, after introduction of the impurities for forming the intrinsic base region and after the formation of the insulating regions, a thermal oxidation is carried out to provide the gate oxide for the complementary IGFETs. This thermal oxidation results in oxidation enhanced diffusion of the impurities making it difficult to obtain a shallow base profile. In addition, the previous anisotropic, for example plasma, etching adversely affects the quality of the gate oxide. After definition of the insulated gates for the complementary IGFETs, the emitter and collector regions of the bipolar transistor are exposed and a further, in the example described, polycrystalline silicon layer is deposited and patterned to complete the insulated gates and form collector and emitter electrodes. After a first implantation of impurities of the one conductivity, phosphorus ions in the example described, to define the lowly doped drain extension of the n-channel IGFET, further impurities of the one conductivity type, in the example described arsenic ions, are implanted to form the source and drain regions of the n-channel IGFET and to provide the impurities which, after a diffusion or drive-in process, form the emitter region and collector contact so that the same implantation dose and energy is used for the n-channnel source and drain regions and for the emitter region. In addition, of course, the implanted impurities will be subjected to the same drive-in process so that again a compromise has to be reached between the requirements of the bipolar transistor and of the complementary IGFETs.